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About Cadence Design Systems: Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments.
Role: Sr Principle DDR Design Engineer
Location: Austin, Texas
- Experienced ASIC RTL designer responsible for architecting and implementing configurable design IP products. You will address performance improvements to our DDR higher speeds and efficiency requirements for newer DRAM Classes.
- Requires a strong background in chip specification, design, and implementation, including Verilog RTL coding, synthesis and STA experience.
- Previous experience designing configurable IP is a strong plus.
- The person will work in a dynamic, team environment and must be able to work effectively with others on projects. Designer will help determine project schedules, discuss technical requirements with customers, write project specifications and provide training and support on new products/features to the field. The person may interact with marketing, support, verification, sales, and customers.
- BSEE or equivalent and a minimum of 8 years of RTL ASIC design
- Strong command of Verilog language
- Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies
- Ability to handle multiple projects/tasks successfully
- Good oral and written communication skills
We’re doing work that matters. Help us solve what others can’t.
- Knowledge of DDR memory protocol
- Experience designing or integrating IP
- Experience with on-chip fabrics
- Experience with highly configurable designs