The candidate is expected to have familiarity with c, SV based verification environment and must possess good analytical and communication skills.
Position Requirements: BE ( Computer Science Electronics) from a reputed institute with 1-3vyears of experience
Experience in Software Programming / Algorithm.
Experience in C will be preferred.
Experience with Hardware Design, Verification
Experience in Verilog/System Verilog/UVM/C/C++
Working experience with standard protocols such as USB, Ethernet and DisplayPort"will be helpful
Experience with development and verification using SV, UVM and C will be a plus.
This position requires leading VIP product development and becoming technical expert in protocol and standard methodologies such as UVM. The position requires excellent communication skills to interact with multiple product groups within Cadence and the ability to ramp up on new technologies quickly and independently.
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