Principal Verification Solutions Engineer

Location: Austin / Texas

Job type

Employment type: Full-Time

Pay: Competitive/hour

Search Button I'm interested

Job description

Req#: R29753

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Sorry, Cadence is not providing work authorization sponsorship, including OPT or F1, for this position.

Design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization.

Independently handle verification of complex modules or own significant piece in subsystem / SOC based verification. Define methodology for subsystem/SOC verification. Mentor less experienced engineers to bring them up as independent verification engineer. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.

Sorry, Cadence is not providing work authorization sponsorship, including H1, OPT or F1, for this position.

Required experience

  • Worked on Subsystem / SOC level verification projects
  • Experience in ARM based designs.
  • In-depth knowledge SV-UVM
  • Expertise in architecting, design and development of scalable verification environments from scratch. Define verification architecture and verification strategy
  • Expertise in verification test plan development, test cases coding; Execute and debug test cases to achieve functional and code coverage goals
  • Experience in C based testcase development
  • Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.
  • Strong problem solving skills. Exhibit discipline, thoroughness and methodical approach in solving problems
  • Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
  • Experience in mentoring junior engineers
  • Self-driven and committed individual who can work in a fast paced project environment
  • Prior experience with Cadence tools and flows is highly desirable
  • Familiarity with ARM/CPU architectures is a plus
  • Experience in developing c-based test cases for SOC verification
  • Experience with assembly language programming
  • Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
  • Embedded C code development and debug
  • Formal Verification experience
  • Cadence verification tool experience

Must be able to obtain and maintain a Department of Defense classified clearance.

We’re doing work that matters. Help us solve what others can’t.

By submitting your interest in this job, you agree to receive text notifications with additional steps to complete your job application. You will receive up to 6 messages from the number "63879". Message & data rates may apply. Please refer to our privacy policy for more information.

About company

Cadence Design Systems, Inc., headquartered in San Jose, California, in the North San Jose Innovation District, is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Sy...
Search Button I'm interested

Not interested?

Search jobs

SHOW OPEN JOBS NEAR ME

Powered by Talentify