Sorry, Cadence is not providing work authorization sponsorship, including OPT or F1, for this position.
Design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization.
Independently handle verification of complex modules or own significant piece in subsystem / SOC based verification. Define methodology for subsystem/SOC verification. Mentor less experienced engineers to bring them up as independent verification engineer. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.
Sorry, Cadence is not providing work authorization sponsorship, including H1, OPT or F1, for this position.
Must be able to obtain and maintain a Department of Defense classified clearance.We’re doing work that matters. Help us solve what others can’t.
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