At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Required Skills and Experience:
We’re doing work that matters. Help us solve what others can’t.
- 5+ years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Experience in mentoring junior engineer
- Excellent knowledge of computer architecture and design verification fundamentals
- Some experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
- Experience in developing complex test bench in SystemVerilog using OVM/UVM methodology
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Some experience with assembly language programming required
- Excellent written and oral communication skills necessary
- Candidate must be self-motivated and capable of working independently or as part of a team
- Must have exp. of mentoring/ leading a small team.