Principal Design Engineer

Location: Pune / Maharashtra

Job type

Employment type: Full-Time

Pay: Competitive/hour

Search Button I'm interested

Job description

Req#: R26130

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Required Skills and Experience

  • 5+ years of design verification experience
  • BS (or higher) in EE/Computer Engineering
  • Experience in mentoring junior engineer
  • Excellent knowledge of computer architecture and design verification fundamentals
  • Some experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
  • Experience in developing complex test bench in SystemVerilog using OVM/UVM methodology
  • Exposure to scripting languages like Perl, Unix shell or similar languages
  • Some experience with assembly language programming required
  • Excellent written and oral communication skills necessary
  • Candidate must be self-motivated and capable of working independently or as part of a team
  • Must have exp. of mentoring/ leading a small team.
We’re doing work that matters. Help us solve what others can’t.

By submitting your interest in this job, you agree to receive text notifications with additional steps to complete your job application. You will receive up to 6 messages from the number "63879". Message & data rates may apply. Please refer to our privacy policy for more information.

About company

Cadence Design Systems, Inc., headquartered in San Jose, California, in the North San Jose Innovation District, is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Sy...
Search Button I'm interested

Not interested?

Search jobs

SHOW OPEN JOBS NEAR ME

Powered by Talentify