Principal Application Engineer - Synthesis/STA/DFT

Location: San Jose / California

Job type

Employment type: Full-Time

Pay: Competitive/hour

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Job description

Req#: R31089

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This individual is the primary focal point for technical issues, questions, and discussions for a given project. Leads technical discussions with customers and is the primary technical interface with the Cadence PM. Capable of influencing outcomes among customers, R&D and Cadence technical team members. * Helps to mentor other designers regarding technical topics for a given project. * Good consulting/client skills. * Deliver results with minimal day-to-day guidance. * Review, document and resolve project technical issues. Escalation of issues to Project Management when appropriate. * Must have an understanding of Cadence semi-custom IC tools. Experience with competitive tools beneficial. * Design Reviews: guides and directs design reviews; final authorization on design issues. * Skill Improvement: helps to identify technical skills that should be developed. Helps to identify technical skills that are needed, but not yet available for a given project. * Change management: assesses the technical impact of changes to include feasibility and estimating the effort associated with implementing the change. * Design Process: leads process improvement initiatives for technical projects. Provides technical support to PM when developing business case for process improvement projects.

We need a pro-active, enthusiastic, customer-facing solution engineer who is an expert in circuits, design and timing analysis. This person will be focused on working with customer in Signoff solution space.

 The ideal candidate should have: 

(1) Understands ASIC Design implementation process and steps

(2) Strong hands-on experience with Synthesis (Genus, RTL Compiler, Design Compiler)

(3) Exposure and experience with Test products (Modus, Encounter Test, Logic Vision,  DFT Compiler etc)

 (4) Experience with EDA tools in the IC digital implementation & signoff flows (STA tools)

 (5) Strong STA and SDC debugging abilities are required.

 (6) Low power analysis, Clock design/analysis and hands-on 16/14nm experience a plus.

 (7) Ability to understand and write RTL (System Verilog, Verilog, VHDL)

  

Requirements:

(1) Requires a BS or MS in EE with 10+ years industry related experience in design and EDA (Digital Implementation/Signoff)

(2) Experience using Digital software with at least one major EDA vendor flow. Automation skills using Perl, Tcl and shell scripting essential 

(3) Strong analytical & analysis skills covering digital implementation is critical. 

(4) Proven track record and experience working in a fast paced environment 

(5) Excellent customer interaction & presentation skills

Should have exposure in:
* Clock Distribution Management * Power Planning * Top-Level timing closure.Block Design: * Timing Verification * Block level Place and Route * Xtalk analysis and fixing * Physical VerificationChip Assembly * Chip Level Place and Route * Physical Verification * Final Post Processing Steps (to generate the GDSII) * Timing VerificationLEC Verification from gate-level netlist through physical design.Signal Integrity * Familiarity with SI affects on high-speed designs

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About company

Cadence Design Systems, Inc., headquartered in San Jose, California, in the North San Jose Innovation District, is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Sy...
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