Principal AE, Memory IP Applications

Location: San Jose / California

Job type

Employment type: Full-Time

Pay: Competitive/hour

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Job description

Req#: R29590

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Principal AE, Memory IP

Job Description

The Cadence IP team develops industry leading IPs that enable our customers in a variety of markets - from the endpoint to the edge to the cloud. At Cadence we’re helping set the standard on IP products that get integrated in SoCs that power the world’s Data Centers, Automobiles, Cloud and Wireless Systems. We offer amazing opportunities to grow, no matter where you are in your career.

We are growing our Silicon Valley team and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence, we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged?  Join the High-Performance Culture at Cadence.

As a Principal Applications Engineer, you will use your knowledge of different memory interface standards to work with current and future customers to help develop their ideas into reality.  You will be part of the Technical Field Organization helping educate customers and providing solutions using our DDR IP portfolio.  Our memory PHY and controller IPs are used in data centers, mobile devices, automobiles and consumer devices.

Responsibilities include:

Technical support for presales and post sales of Memory IP

Present Cadence’s IP portfolio and capabilities to prospective customers

Performance evaluations of Cadence memory IP and development of related infrastructure

Serve as a product expert in memory controller and PHY IPs and protocols

Work closely with IP Sales staff, marketing and R&D teams to win opportunities

Provide quick-turn product specific technical applications engineering support to our customers, field teams, definers and designers

Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal and/or external publication

10-25% Travel will be required


BS in EE, CE or related equivalent with 8+ years of work experience or MS in EE, CE or related equivalent with 6+ year of work experience

Experience with simulation and synthesis tools

Experience on memory subsystem verification and/or performance analysis

Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design

Knowledge of one or more DRAM protocols – DDR4/5, LPDDR4/5, HBM2, GDDR6

Knowledge of AXI, DFI and MIPI protocols is a plus

Working knowledge of memory controller and memory PHY preferred

Individual leadership and initiative to manage pre-sales accounts

Excellent presentation skills and verbal/written communication skills is a must

We’re doing work that matters. Help us solve what others can’t.

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About company

Cadence Design Systems, Inc., headquartered in San Jose, California, in the North San Jose Innovation District, is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Sy...
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