Work closely with R&D on understanding customer design requirements. Write synthesizable designs (RTL) in Verilog/SV/VHDL to test various domains and features of Genus.
Synthesize the designs using Cadence synthesis solution Genus. Perform QoR analysis and debugging of synthesis results. Perform Equivalence checking of the Synthesis netlist. Review feature specifications and write test plans for new features. Contribute to make the solution better by working with RnD teams.
Good understanding of RTLs and proficiency in SV/Verilog/VHDL coding.
Strong knowledge of Synthesis and timing concepts.
Working knowledge of Conformal LEC/Formality.
Basic scripting skills will be added advantage.We’re doing work that matters. Help us solve what others can’t.
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