At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Skill Requirements:
- Minimum 4-year experience in RTL design in Verilog / System Verilog, with a strong focus on floating-point / fixed-point datapath components.
- Familiarity with verification with UVM and Testbench generation a strong plus.
- Excellent communication skills (publications, presentations).
- Experience with clock domain crossing, closing timing and meeting power consumption goals in large designs in advanced technology nodes (sub-16nm geometries).
- Scripting language experience such as Python, Perl, TCL, SystemC etc.
- Debugging experience in simulation, emulation, and system bring-up in collaboration with Verification, Emulation, Physical Design, Firmware teams, etc.
We’re doing work that matters. Help us solve what others can’t.
- Implement and deliver verified RTL blocks based on architectural and micro-architectural requirements.
- Write datasheets, architectural and micro-architectural documents.
- Support the Digital Verification, Physical Design, and Firmware teams to ensure correctness of the delivered RTL.
- Respond to customer issues related to Lint, CDC, STA, Synthesis, and LEC tools.
- Degree: BE/B.Tech or ME/MTech